JP63299296 (Meiko), JP63299297A (Meiko) and “Manufacturing of Printed Wiring Boards by Ultra-high Speed Electroforming” by Norio Kawachi (Meiko) et al, Printed Circuit World Convention, June 1990 describe the use of the electroforming technique in creating circuit boards (printed wiring boards). Electroforming is an additive process that involves obtaining a replica (negative) of a metal carrier by electrolytic deposition of a metallic film using the carrier as a cathode. A patterned photo-resist is used to limit the electro-deposition of material to the exposed areas of the cathode. The documents additionally teach a transfer lamination process in which the deposited metal and photo-resist are laminated to a substrate and the master is removed leaving a deposited metal photo-resist substrate combination. JP63299296 (Meiko), JP63299297A (Meiko) additionally disclose the electrolytic deposition of a copper plate layer on the master before the deposition of the metal. This copper layer is transferred in the transfer-lamination process and is removed by etching.
U.S. Pat. No. 6,284,072 discloses the formation of patterning on a conductive carrier by micro-moulding. An insulating material is embossed to create a pattern that limits the electro-deposition of metal to exposed areas of the conductive carrier.
Electroforming is used in the semiconductor industry in the creation of printed wiring boards and large scale interconnects on bulk semiconductors. Electroforming is not accurate enough for use in bulk semiconductor device processing which is at a scale of nanometres.
The bulk semiconductor industry typically uses metal sputtering with UV photo-lithography to define small scale metal interconnects.
Organic semiconductors are a fairly recent development compared with bulk semiconductors. Devices made from organic semiconductors cannot match the speed or efficiencies of bulk semiconductors, but they have other distinct advantages. They are suitable for large area processing and can be used on flexible substrates. They have therefore attracted a lot of attention for their potential application in display device technologies, particularly their use in thin film transistors for use in active matrix displays.
An organic transistor typically has metallic source, gate and drain electrodes. A thin film of organic semiconductor forms a channel interconnecting the source and drain electrodes, that is separated from the gate electrode by a thin dielectric layer.
As years of research into the creation of bulk semiconductors have been carried out, the organic transistors presently re-use technology developed for bulk semiconductors as these processes are well understood. For example, the metallic electrodes are typically created by metal sputtering.
The inventors have realised that the use of sputtering may be optimal for bulk semiconductors but is sub-optimal for low cost, large area integrated circuits, such as displays incorporating organic thin film transistors.
Sputtering requires a vacuum environment. This is expensive and difficult to implement for large area processes.
Also, to obtain low impedance interconnects using sputtering the interconnects must either be wide or thick. A thick interconnect can create stresses which require controlling, which adds cost. Thick interconnects may limit the resolution of the devices (the number per unit area).
U.S. Pat. No. 6,344,662 describes the creation of a TFT having a hybrid organic-inorganic semiconductor layer. The gate metallization is formed using electron beam evaporation and the metal source and drain are formed separately by vapor deposition. Claim 6 states, without further explanation or clarification, that the gate electrode is produced by a process selected from the group consisting of evaporation, sputtering, chemical vapor deposition, electrodeposition, spin coating, and electroless plating.